interface sram_if # (
    parameter integer C_S00_AXI_DATA_WIDTH   = 32,
    parameter integer C_S00_AXI_ADDR_WIDTH   = 4,
    parameter integer C_M00_AXIS_TDATA_WIDTH = 32,
    parameter integer C_M00_AXIS_START_COUNT = 32,
    parameter integer C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
    parameter integer C_M00_AXI_BURST_LEN    = 16,
    parameter integer C_M00_AXI_ID_WIDTH     = 1,
    parameter integer C_M00_AXI_ADDR_WIDTH   = 32,
    parameter integer C_M00_AXI_DATA_WIDTH   = 32,
    parameter integer C_M00_AXI_AWUSER_WIDTH = 0,
    parameter integer C_M00_AXI_ARUSER_WIDTH = 0,
    parameter integer C_M00_AXI_WUSER_WIDTH  = 0,
    parameter integer C_M00_AXI_RUSER_WIDTH  = 0,
    parameter integer C_M00_AXI_BUSER_WIDTH  = 0
) (input logic clk);

   wire                                     m00_axis_aclk = clk;
   wire                                     m00_axis_tvalid;
   wire [C_M00_AXIS_TDATA_WIDTH-1 : 0     ] m00_axis_tdata;
   wire [(C_M00_AXIS_TDATA_WIDTH/8)-1 : 0 ] m00_axis_tstrb;
   wire                                     m00_axis_tlast;
   wire                                     m00_axis_tready;
 
   wire                                     m00_axi_aclk = clk;
   wire [C_M00_AXI_ID_WIDTH-1 : 0         ] m00_axi_awid;
   wire [C_M00_AXI_ADDR_WIDTH-1 : 0       ] m00_axi_awaddr;
   wire [7 : 0                            ] m00_axi_awlen;
   wire [2 : 0                            ] m00_axi_awsize;
   wire [1 : 0                            ] m00_axi_awburst;
   wire                                     m00_axi_awlock;
   wire [3 : 0                            ] m00_axi_awcache;
   wire [2 : 0                            ] m00_axi_awprot;
   wire [3 : 0                            ] m00_axi_awqos;
   wire [C_M00_AXI_AWUSER_WIDTH-1 : 0     ] m00_axi_awuser;
   wire                                     m00_axi_awvalid;
   wire                                     m00_axi_awready;
   wire [C_M00_AXI_DATA_WIDTH-1 : 0       ] m00_axi_wdata;
   wire [C_M00_AXI_DATA_WIDTH/8-1 : 0     ] m00_axi_wstrb;
   wire                                     m00_axi_wlast;
   wire [C_M00_AXI_WUSER_WIDTH-1 : 0      ] m00_axi_wuser;
   wire                                     m00_axi_wvalid;
   wire                                     m00_axi_wready;
   wire [C_M00_AXI_ID_WIDTH-1 : 0         ] m00_axi_bid;
   wire [1 : 0                            ] m00_axi_bresp;
   wire [C_M00_AXI_BUSER_WIDTH-1 : 0      ] m00_axi_buser;
   wire                                     m00_axi_bvalid;
   wire                                     m00_axi_bready;
   wire [C_M00_AXI_ID_WIDTH-1 : 0         ] m00_axi_arid;
   wire [C_M00_AXI_ADDR_WIDTH-1 : 0       ] m00_axi_araddr;
   wire [7 : 0                            ] m00_axi_arlen;
   wire [2 : 0                            ] m00_axi_arsize;
   wire [1 : 0                            ] m00_axi_arburst;
   wire                                     m00_axi_arlock;
   wire [3 : 0                            ] m00_axi_arcache;
   wire [2 : 0                            ] m00_axi_arprot;
   wire [3 : 0                            ] m00_axi_arqos;
   wire [C_M00_AXI_ARUSER_WIDTH-1 : 0     ] m00_axi_aruser;
   wire                                     m00_axi_arvalid;
   wire                                     m00_axi_arready;
   wire [C_M00_AXI_ID_WIDTH-1 : 0         ] m00_axi_rid;
   wire [C_M00_AXI_DATA_WIDTH-1 : 0       ] m00_axi_rdata;
   wire [1 : 0                            ] m00_axi_rresp;
   wire                                     m00_axi_rlast;
   wire [C_M00_AXI_RUSER_WIDTH-1 : 0      ] m00_axi_ruser;
   wire                                     m00_axi_rvalid;
   wire                                     m00_axi_rready;

   clocking axi4_cb @(posedge clk);
        input  m00_axis_tvalid;
        input  m00_axis_tdata;
        input  m00_axis_tstrb;
        input  m00_axis_tlast;
        output m00_axis_tready;
 
        input  m00_axi_awid;
        input  m00_axi_awaddr;
        input  m00_axi_awlen;
        input  m00_axi_awsize;
        input  m00_axi_awburst;
        input  m00_axi_awlock;
        input  m00_axi_awcache;
        input  m00_axi_awprot;
        input  m00_axi_awqos;
        input  m00_axi_awuser;
        input  m00_axi_awvalid;
        output m00_axi_awready;
        input  m00_axi_wdata;
        input  m00_axi_wstrb;
        input  m00_axi_wlast;
        input  m00_axi_wuser;
        input  m00_axi_wvalid;
        output m00_axi_wready;
        output m00_axi_bid;
        output m00_axi_bresp;
        output m00_axi_buser;
        output m00_axi_bvalid;
        input  m00_axi_bready;
 
        input  m00_axi_arid;
        input  m00_axi_araddr;
        input  m00_axi_arlen;
        input  m00_axi_arsize;
        input  m00_axi_arburst;
        input  m00_axi_arlock;
        input  m00_axi_arcache;
        input  m00_axi_arprot;
        input  m00_axi_arqos;
        input  m00_axi_aruser;
        input  m00_axi_arvalid;
        output m00_axi_arready;
        output m00_axi_rid;
        output m00_axi_rdata;
        output m00_axi_rresp;
        output m00_axi_rlast;
        output m00_axi_ruser;
        output m00_axi_rvalid;
        input  m00_axi_rready;
   endclocking

   modport memprt(clocking axi4_cb);
   modport monprt(clocking axi4_cb);
endinterface


